Seattle Pacific University 2014 - 2015 Undergraduate Time Schedule
Time Schedule Home :: 2010-2011 Catalog Home

         << Previous Page |

EE 1210: Introduction to Logic System Design
Introduction to digital logic design including combinational and sequential logic design with Computer Aided Design (CAD)using VHDL hardware description language. Combinational logic covers truth tables, Boolean algebra, logic gates, circuit minimization, logic maps, multiplexers, decoders, encoders, programmable logic and memories, and more. Sequential logic covers latches, flip-flops, clocks, registers, counters, finite state machines, CPLDs and FPGAs. Emphasis is placed on design techniques. Laboratory exercises include designs using both discrete gates and FPGAs.

TermCRNCredits Instructor(s)DaysTime DatesLocationFeesOpen
Autumn 1282 5 Don Peter
M,W,F
Final: Tu
8:00AM-9:20AM
8:00AM-10:00AM
09/26-12/02
12/06-12/06
Otto Miller Hall 225
Otto Miller Hall 225
$5 0 waitlisted Add to Outlook
Grade Modes: (Default) Normal Grading, Audit, Pass/No Credit Instructional Methods: Traditional Note: Full Term
Autumn 7623 5 Don Peter
Arranged
Online-
09/26-12/02
**Online
$5 1 open seat Add to Outlook
Special Approval: Instructor Permission Required Grade Modes: (Default) Normal Grading, Audit, Pass/No Credit Instructional Methods: Online Note: Full Term



Copyright © 2016 Seattle Pacific University.
Web Content Disclaimer.
General Information: (206) 281-2000
3307 Third Avenue West, Seattle, WA 98119-1997, U.S.A.

How did this page do?
Click here to rate it!