Seattle Pacific University 2012 - 2013 Undergraduate Time Schedule
Time Schedule Home :: 2012-2013 Catalog Home

         << Previous Page |

EE 1210: Introduction to Logic System Design
Introduction to digital logic design including combinational and sequential logic design. Combinational logic covers truth tables, Boolean algebra, logic gates, Karnaugh maps, multiplexers, decoders, encoders, programmable logic and memories. Sequential logic covers latches, flip-flops, clocks, registers, counters, finite state machines, CPLDs and FPGAs. Special emphasis is placed on design techniques. Laboratory exercises include designs using both discrete gates and FPGAs. Extra fee.

TermCRNCredits Instructor(s)DaysTime DatesLocationFeesOpen
Autumn 11161 5 Kevin Bolding
M,W,F
Final: Tu
1:30PM-2:50PM
1:00PM-3:00PM
09/25-12/01
12/05-12/05
Otto Miller Hall 225
Otto Miller Hall 225
$20 - Add to Outlook
Grade Modes: (Default) Normal Grading, Audit, Pass/No Credit Instructional Methods: Traditional Note: Full Term
Autumn 1282 5 Kevin Bolding
M,W,F
Final: Tu
11:00AM-12:20PM
10:30AM-12:30PM
09/25-12/01
12/05-12/05
Otto Miller Hall 225
Otto Miller Hall 225
$5 - Add to Outlook
Grade Modes: (Default) Normal Grading, Audit, Pass/No Credit Instructional Methods: Traditional Note: Full Term



Copyright © 2017 Seattle Pacific University.
Web Content Disclaimer.
General Information: (206) 281-2000
3307 Third Avenue West, Seattle, WA 98119-1997, U.S.A.

How did this page do?
Click here to rate it!